In many electronic circuits, it is necessary to generate internal clocks with predetermined phase relationships to a reference clock. Clock synchronization circuits such as phase locked loops (PLLs) or delay locked loops (DLLs) are often used to generate an internal clock signal that is synchronized, e.g., in phase, with a reference clock signal.
FIG. 1 is a block diagram of a conventional DLL 100. The DLL 100 includes a voltage controlled delay line (VCDL) 104 that receives a reference clock signal REF, and in response, generates a feedback clock signal FB having a delay relative to the REF signal that is based on a voltage magnitude of a control voltage VCTRL. The DLL 100 also includes a phase detector (PD) 108 that receives the REF and FB clock signals and generates UP and DN control signals for charge pump 112. The respective values of the UP and DN signals depend on the phase difference between the REF and FB clock signals. For example, if the FB clock signal leads the REF clock signal, the DN signal goes high and remains high until the next rising edge of the REF clock signal, while the UP signal remains low. If the FB clock signal lags the RCLK clock signal, the UP clock signal goes high and remains high until the next rising edge of the FB clock signal, while the DN signal remains low. The UP and DN signals increase and decrease the output CPOUT of the charge pump 112. As a result, CPOUT of the charge pump is adjusted based on the phase difference between the REF and FB clock signals.
A loop filter 114 provides the VCTRL voltage to a bias generator 116 in accordance with the CPOUT output from the charge pump 112. The loop filter is typically a low pass filter that filters out high-frequency noise of the CPOUT output to provide the VCTRL voltage. For example, in some embodiments of the invention, the loop filter 114 includes a capacitor. The bias generator buffers the VCTRL voltage and provides a VBIAS voltage to the VCDL 104 to adjust the variable delay of the VCDL 104 until the REF and FB clock signals are in phase, as detected by the PD 108. Under this condition, the DLL 100 is referred to as being “locked.”
The bias generator 116 included in the DLL 100 further applies a constant VBIAS voltage to the VCDL 104 and is coupled to the PD 108 to disable it during initialization of the DLL 100. When the PD 108 is disabled, the bias generator 116 generates a VBIAS voltage having a constant voltage that is used to set an initial voltage applied to the VCDL 104. In response, the VCDL 104 generates a FB signal having an initial delay set by the voltage of the constant VBIAS voltage. After the start-up operation, and the DLL 100 has been initialized, the constant VBIAS voltage is no longer provided to the VCDL 104 and the PD 108 is enabled by the bias generator 116. Following initialization, the DLL 100 operates as previously described.
The amount of time required to eliminate the phase difference between the FB and REF clock signals depends, among other things, on the constant VBIAS voltage applied during initialization of the DLL 100 to set an initial delay of the VCDL 104. As a result, selecting a constant voltage for the VBIAS voltage that reduces the time required to eliminate the phase difference is desirable. If the voltage of the VBIAS voltage is not selected properly, it may require a relatively long period of time for the DLL 100 to eliminate the phase difference. Moreover, the amount of time to obtain a locked timing condition will be affected by process variations in semiconductor integrated circuits (ICs). The process variations refer to variations in semiconductor fabrication processing steps such as, for example, ion implantation, deposition, lithography and etching that affect the performance of ICs. Voltage and temperature variations also affects the performance of ICs. As a result, the initial voltage of the constant VBIAS signal may be sufficient to facilitate the DLL 100 quickly obtaining lock under some voltage, temperature, and frequency, operating conditions, but given a different set of operating conditions, it may take significantly longer for the DLL 100 to obtain lock.
As known, a memory may enter a power-saving mode where various non-essential memory circuitry are disabled to reduce power consumption during periods of inactivity. A memory recovers from a power-saving mode when memory activity increases, re-enabling the previously disabled circuitry in order to perform memory functions. A typical example of circuitry that is disabled during power-saving mode is clock circuitry, such as DLL 100. When the DLL 100 is re-enabled after being disabled, however, the delay settings of the VCDL 104 may no longer provide the locked condition. During the recovery operation, the VCDL 104 needs to be adjusted accordingly to re-obtain a locked condition. As a result, before a memory can begin normal operation time is wasted during recovery from a power-saving mode to re-obtain a locked timing conditions for the DLLs.
Therefore, there is a need for a circuit that provides an initial control voltage for clock synchronization circuits upon power-up, and during recovery from power-saving modes that facilitates rapid synchronization under various operating conditions.